Decision trees, inside the decision window
Decision tree models are a standard choice for latency-critical applications. They are small, well understood and quick to train. The hard part is running them fast enough, at enough scale, to matter.
VOLLO Trees accelerates inference for streaming decision tree models on FPGAs. It delivers lower latency and higher throughput density than any other audited platform, and lets you run more models simultaneously on a single chip.
Independently audited by STAC1.
Why VOLLO Trees?
- Lowest latency: The lowest latency inference for streaming decision tree models, independently audited by STAC1.
- Highest throughput: More inferences per second than any other audited system, proven by STAC1.
- Highest energy-efficiency: More inferences/sec/kW than any other audited system, verified by STAC1.
- More models per chip: Run multiple models simultaneously on a single FPGA.
- Easy to adopt: Compile ONNX models directly to supported FPGAs. No FPGA expertise or tools required.
- Quick to deploy: Use PCIe accelerator cards for rapid adoption, or FPGA netlists for integration into your own design.
VOLLO Evaluation
Any ML developer can evaluate VOLLO Trees without new hardware, FPGA expertise or a licence.
The VOLLO Trees compiler and Virtual Machine are freely available. Compile your ONNX decision tree models and get an accurate estimate of how they will perform on supported FPGA boards. Everything runs on your own machine, so your models and data never leave your control.
Built for performance
VOLLO Trees runs on FPGAs, delivering consistent low latency where CPU-based inference struggles to keep pace with streaming data.
For a full list of supported cards, visit the VOLLO Trees User Guide.