Setting a New Record for Single-Digit Microsecond Latency Inference in Capital Markets

myrtle.ai’s VOLLO™ accelerator posts the lowest 99th-percentile latencies ever published on the STAC-ML Markets (Inference) Tacana benchmark — beating every public submission, including NVIDIA’s GH200 Grace Hopper Superchip.

Key results at a glance

• New world record: lowest p99 latency ever published on the STAC-ML Tacana suite, across every model and configuration submitted.
• Up to 4.0× faster than myrtle.ai’s own 2023 FPGA submission — the one NVIDIA’s April 2026 post used as its FPGA comparison point.
• Up to 3.1× faster than NVIDIA’s newest GH200 Grace Hopper GPU result on the same benchmark.
• One FPGA card, not four: the 2026 result needs a single Silicom Artena card, versus four cards in the 2023 submission.

In algorithmic trading, shaving microseconds off the response to a market event is still the difference between capturing an opportunity and watching a competitor take it. To keep pace with high-speed electronic markets, latency-sensitive firms have long relied on purpose-built silicon — FPGAs, GPUs, and ASICs — to run machine learning inference directly against live market data.

In April 2026, NVIDIA published a post on this very topic, Achieving Single-Digit Microsecond Latency Inference for Capital Markets, announcing single-digit microsecond 99th-percentile (p99) latencies for LSTM inference on the GH200 Grace Hopper Superchip in the STAC-ML™ Markets (Inference) Tacana benchmark. In positioning those results, NVIDIA referenced “recent benchmark submissions on FPGA for Tacana” that had “reported single-digit microsecond latencies for two LSTM sizes” — a nod to myrtle.ai’s VOLLO™ result from April 2023 (SUT ID MRTL230426).

That comparison was accurate. It was also three years out of date.

On 24 April 2026, STAC published myrtle.ai’s latest, fully audited STAC-ML Markets (Inference) Tacana result (SUT ID: MRTL260323). Running on a single Silicom Artena FPGA card in a Supermicro server, VOLLO didn’t just improve on its 2023 numbers — VOLLO posted the lowest p99 latency ever recorded on the Tacana suite, for every model, at every configuration submitted, ahead of every other public entry to date, GPU or FPGA. This post walks through those results, shows how they compare with both VOLLO’s prior submission and the newest GPU numbers on the board, and explains what changed under the hood to get there.

STAC-ML benchmarking in financial services

STAC-ML Markets (Inference) is the industry-standard benchmark for running inference on live market data, designed by quants and technologists from many of the world’s leading financial firms. It reports the latency, throughput, resource efficiency, and quality of any technology stack running a set of standardized LSTM workloads, independent of the underlying hardware architecture or numerical precision. The Tacana suite specifically models sliding-window inference — the pattern used when a model re-evaluates a fixed history of ticks or bars every time a new one arrives — and it allows implementations to reuse computation and transfer only the newest timestep to the accelerator, rewarding architectures purpose-built for the job.

Because the benchmark is designed and governed by practitioners from major trading firms, STAC-ML results carry real weight in technology selection. For co-located trading infrastructure, where the outcome of an order can turn on microseconds, a STAC-ML report is one of the few objective, apples-to-apples ways to compare hardware and software stacks before committing budget to either.

myrtle.ai’s new STAC-ML results

The full submission — STAC-ML Markets (Inference) Pack for myrtle.ai VOLLO™ (Rev C), running on a single Silicom Artena card (AMD Versal Premium VP1802 FPGA) in a Supermicro AS-2015CS-TNR server — posted the following audited 99th-percentile latencies on the Tacana suite:

These figures include the full PCIe round trip to and from the accelerator — roughly 1 µs of the total — so they represent real, end-to-end inference latency, not a theoretical compute-only number.

Per STAC’s own report, compared with every other public submission to the Tacana suite, across all three models and every NMI configuration tested, this is the lowest p99 latency ever reported for each of those models, regardless of number of model instances. Three barriers fell in the process:

Comparison with myrtle.ai’s previous submission

The FPGA result NVIDIA referenced in April was myrtle.ai’s — SUT ID MRTL230426, audited in 2023 on four BittWare IA-840f cards (Intel Agilex FPGAs) in a BittWare TeraBox 1402B server, running VOLLO SDK v0.2.0 at bfloat16 precision. It was a solid result for its time: 5.07 µs p99 for LSTM_A, 6.89 µs for LSTM_B, 31.0 µs for LSTM_C.

Three years, and a full generation of silicon and compiler improvements later, VOLLO’s new submission (running VOLLO SDK 27.0.0, on a single AMD VP1802 FPGA card rather than four Agilex cards) is dramatically faster and more accurate:

Beyond the latency gains, the 2026 submission also uses a fraction of the hardware footprint of its 2023 predecessor: one FPGA card instead of four, in a smaller, more power-efficient 2U server.

Comparison with NVIDIA’s newest GPU result

NVIDIA’s April 2026 post reported the following p99 latencies for the GH200 Grace Hopper Superchip on the same Tacana suite (SUT ID SMC250910), at FP16 precision:

STAC-ML Tacana — 99th-percentile latency, NMI=1 (log scale, lower is better)

Source: STAC Reports MRTL230426, MRTL260323, and SMC250910 (all figures 99th-percentile, NMI=1)

For context, myrtle.ai’s 2023 FPGA submission — the one NVIDIA’s post used as the FPGA comparison point — was itself roughly on par with the GH200 numbers on LSTM_A and LSTM_B, and about 2× slower on LSTM_C. NVIDIA’s characterization of “matching or exceeding” FPGA performance was a fair read of the board as it stood at the time. It just wasn’t reading the current board. VOLLO’s new submission outpaces both the 2023 FPGA result it was compared against and the GH200 result it was published alongside, on every model in the suite.

As always with STAC-ML, anyone evaluating these numbers is encouraged to read the full audited reports rather than rely on any vendor’s summary — myrtle.ai’s included. The STAC methodology groups submissions into precision/error “weight classes” for a reason, and the full reports (available at stacresearch.com/MRTL260323 and docs.stacresearch.com/SMC250910) contain the error, throughput, and efficiency detail needed to make a like-for-like judgment for any given workload.

What changed under the hood

The result didn’t come from exotic new hardware alone. It came from three years of customer-driven engineering on top of a compiler-first approach to FPGA inference:

• PyTorch in, FPGA out. VOLLO compiles standard PyTorch (or TensorFlow, or ONNX) models directly into an FPGA program. For this benchmark, the sliding window used by the Tacana suite is expressed as ordinary PyTorch state — the rest of the compilation is automatic. No RTL, no FPGA toolchain, no hardware expertise required of the ML engineer.
• A single accelerator, doing more. Where the 2023 result needed four FPGA cards to hit single-digit microseconds, the 2026 result does it on one Silicom Artena card built around a single AMD Versal Premium VP1802 Adaptable SoC — 3.36M LUTs and 994 Mb of on-chip memory, connected over PCIe Gen5. Multiple model instances share the chip through VOLLO’s support for multi-model programs, each given its own subset of cores at compile time.
• A driver that gets out of the way. The inference driver is a single-threaded Rust program that queues requests through the VOLLO Runtime’s C API and polls for results — no batching, no external orchestration layer standing between a market data tick and an inference result.

This is the same VOLLO flow — PyTorch or TensorFlow in, a bitstream on commodity FPGA silicon out — that has now logged hundreds of thousands of hours in live production trading at some of the world’s largest quantitative firms, with continual performance and efficiency improvements delivered to subscribers throughout that time. This audit is simply the independently verified proof point of gains myrtle.ai’s customers have already been living with.

Three years in production

The gains in this audit did not appear overnight. The same VOLLO compiler and runtime that produced this result has, since its first Tacana audit three years ago, logged hundreds of thousands of hours in live production trading at some of Wall Street’s leading quantitative firms — with continual performance and efficiency improvements shipped to subscribers throughout that time. myrtle.ai’s finance customers alone reported over $14.2bn in combined net revenue in 2024.

Get started with VOLLO

VOLLO’s evaluation path doesn’t require FPGA hardware, an FPGA license, or FPGA expertise: